1. Field of the Invention
The present invention relates to a semiconductor device including a MOSFET of an LDD (Lightly Doped Drain) structure, particularly, to a semiconductor device including a MOSFET of an LDD structure of a so-called "polycide gate electrode", which comprises a poly-Si layer and a refractory metal such as W, Ti or Ta or a metal silicide layer, and a method of manufacturing the same.
2. Description of the Related Art
FIG. 1 shows the conventional NMOSFET of an LDD structure. For manufacturing the MOSFET shown in the drawing, a gate oxide film 2 is deposited first on a p-type semiconductor substrate 1, followed by forming a poly-Si layer 3 on the gate oxide film 2. Then, As ions are implanted, followed by activating the implanted As ions by heat treatment and subsequently forming a metal silicide layer 4. Further, an anisotropic etching is applied so as to form a gate electrode structure. Then, impurity ions are implanted at a low concentration to form a diffusion layer 6 for the LDD structure, followed by forming a SiO.sub.2 layer by CVD. Further, anisotropic etching is applied to the CVD SiO.sub.2 layer so as to form a sidewall spacer 5 for the gate electrode, followed by ion implantation for forming source/drain regions 7. The problems summarized below are inherent in the conventional MOSFET shown in FIG. 1:
1. A heat treatment such as annealing is applied to a laminate structure consisting of the poly-Si 3 and the metal silicide layer 4 having a high melting point. During the heat treatment, the metal atoms within the metal silicide layer 4 are diffused into the gate oxide film 2 through the grain boundary within the poly-Si layer 3 so as to lower the breakdown voltage of the gate oxide film 2. The problem is serious in the case where the poly-Si layer 3 is made thin, leading to a serious defect in the case of flattening the surface morphology for miniaturizing the elements.
2. The LDD structure is effective for moderating the electric field around the drain region so as to improve the reliability of the MOSFET. In the conventional method in which the sidewall spacer 5 is formed of CVD.SiO.sub.2, hot electrons derived from stress are trapped in the CVD.SiO.sub.2 layer 5 positioned on the N.sup.- type region, leading to a high resistance at the boundary between the CVD.SiO.sub.2 layer 5 and the diffusion layer 6. This brings about the deterioration inherent in the LDD structure.